An integrated circuit (“IC”) is a device (e.g., a semiconductor device) or electronic system that includes many electronic components, such as transistors, resistors, diodes, etc. These components are often interconnected to form multiple circuit components, such as gates, cells, memory units, arithmetic units, controllers, decoders, etc. An IC includes multiple layers of wiring that interconnect the IC's electronic and circuit components.
Design engineers design ICs by transforming logical or circuit descriptions of the ICs' components into geometric descriptions, called design layouts. Design layouts typically include (1) circuit modules (i.e., geometric representations of electronic or circuit IC components) with pins and (2) interconnect lines (i.e., geometric representations of wiring) that connect the pins of the circuit modules. In this fashion, design layouts often describe the behavioral, architectural, functional, and structural attributes of the IC. To create design layouts, design engineers typically use electronic design automation (“EDA”) applications. These applications provide sets of computer-based tools for creating, editing, analyzing, and verifying design layouts. The applications also render the layouts on a display device or to storage for displaying later.
Fabrication foundries (“fabs”) manufacture ICs based on the design layouts using a photolithographic process. Photolithography is an optical printing and fabrication process by which patterns on a photolithographic mask (i.e., “photomask,” or “mask”) are imaged and defined onto a photosensitive layer coating a substrate. To fabricate an IC, photomasks are created using the IC design layout as a template. The photomasks contain the various geometries or shapes (i.e., features) of the IC design layout. The various geometries or shapes contained on the photomasks correspond to the various base physical IC elements that comprise functional circuit components such as transistors, interconnect wiring, vertical interconnect access (via) pads, as well as other elements that are not functional circuit elements but are used to facilitate, enhance, or track various manufacturing processes. Through sequential use of the various photomasks corresponding to a given IC in an IC fabrication process, a large number of material layers of various shapes and thicknesses with various conductive and insulating properties may be built up to form the overall IC and the circuits within the IC design layout.
As more circuit features are packed into an IC design layout (e.g., manufacturing processes at feature sizes of 22 nm and below), the resolution of the photolithographic process makes it extremely difficult to fabricate the geometries or shapes on a single lithography mask. The difficulty stems from constraining factors in traditional photolithographic processes that limit the effectiveness of current photolithographic processes. Some such constraining factors are the lights/optics used within the photolithographic processing systems. Specifically, the lights/optics are band limited due to physical limitations (e.g., wavelength and aperture) of the photolithographic process. Therefore, the photolithographic process cannot print beyond a certain minimum width of a feature, minimum spacing between features, and other such physical manufacturing constraints.
For a particular layer of the IC fabrication process, the pitch specifies the sum of the width of a feature and the space on one side of the feature separating that feature from a neighboring feature on the same layer. The minimum pitch for a layer is the sum of the minimum feature width and the minimum spacing between features on the same layer. Depending on the photolithographic process at issue, factors such as optics and wavelengths of light or radiation restrict how small the pitch may be made before features can no longer be reliably printed to a wafer or mask. As such, the smallest size of any features that can be created on a layer of an IC is limited by the minimum pitch for the layer.
FIG. 1 illustrates a typical pitch constraint of a photolithographic process. In FIG. 1, a pitch 110 acts to constrain the spacing between printable features 120 and 130 of a design layout. While other photolithographic process factors such as the threshold 140 can be used to narrow the width 150 of the features 120 and 130, such adjustments do not result in increased feature density without adjustments to the pitch 110. As a result, increasing feature densities beyond a certain threshold is infeasible via a pitch constrained single exposure process.
To enhance the feature density, the shapes on a single layer can be manufactured on two different photolithographic masks. This approach is often referred to as “Double Patterning Lithography (DPL)” technology. FIG. 2 illustrates an example of this approach. In FIG. 2, a design layout 205 specifies three features 210-230 that are pitch constrained and therefore cannot be photolithographically printed with a conventional single exposure process. Analysis of the characteristics (e.g., the band limitation) of the available photolithographic process and of the design layout 205 results in the decomposition of the design layout 205 into a first exposure 240 for printing features 210 and 230 and a second exposure 250 for printing feature 220. As such, the features 210 and 230 are assigned to a first photomask for printing during the first exposure 240 and feature 220 is assigned to a second photomask for printing during the second exposure 250.
FIGS. 3A and 3B illustrate two different manners of using DPL technology. FIG. 3A illustrates sending different shapes of a layer to two different masks. In contrast, FIG. 3B illustrates decomposing one shape into several smaller shapes to send them to two different masks. Specifically, FIG. 3A illustrates sending five shapes 301-305 of a design layout 300 to two different masks. The shape pairs of the shapes 301 and 302; the shapes 302 and 303; the shapes 303 and 304; and the shapes 304 and 305 are all pitch constrained. Therefore, the two shapes of each pair must be sent to two different masks 310 and 315. Accordingly, the shapes 301 and 303 are sent to a first mask 310. That is, the shapes 301 and 303 are printed during a first exposure in order to produce contours 320. Similarly, the shapes 302, 304, and 305 are sent to a second mask 315. That is, the shapes 302, 304, and 305 are printed during a second exposure in order to produce contours 325. The resulting union of the contours 320 and 325 generates pattern 330 that is sufficient to approximately reproduce the original design layout 300.
FIG. 3B illustrates a decomposition of a pattern 340 defined in a layer of design layout for fabricating an IC into two sets of polygons 350 and 360. Each such decomposed set of polygons 350 and 360 is printed during an exposure of a multiple exposure photolithographic printing process. For instance, polygon set 350 is printed during a first exposure in order to produce contours 370 and polygon set 360 is printed during a second exposure in order to produce contours 380. The resulting union of the contours 370 and 380 generates pattern 390 that is sufficient to approximately reproduce the original pattern 340. Accordingly, a valid decomposition solution is such that the union of the contours created/printed from each exposure closely approximates specifications within the original design layout and satisfies multi-exposure photolithographic printing constraints (e.g., the band limit and the target layout specified within the design layout) with no resulting “opens”, “shorts”, or other printing errors materializing on the physical wafer.
To use DPL technology, the layout designers need to follow a set of design rules or constraints while designing the layout such that the shapes on a single design layer can be successfully fabricated using two different masks. Some available EDA tools assign two colors (e.g., red and green) to the shapes to identify the two masks with which the shapes will be fabricated. Each shape on a design layer begins with its color unassigned. The EDA tool assigns one of the two colors to each shape on the layer. Shapes that have been assigned to the same color must be spaced apart by at least a certain minimum distance specified by the design rules. Typically, the required minimum spacing between shapes assigned to the same color is greater than the required minimum spacing between two shapes with different colors because shapes with different colors are fabricated using different masks, bypassing the limitations of the single-exposure photolithographic process. In this application, the required minimum spacing between shapes assigned to the same color is referred to as a minimum same color spacing. The required minimum spacing between two shapes with different colors is referred to as a minimum spacing.
Since a pitch specifies the sum of the width of a shape (i.e., feature) and the space on one side of the shape separating that feature from a neighboring shape, a minimum same color spacing is pitch minus the width of the shape in some embodiments. A specific color that is assigned to a particular shape is arbitrary. However, the assignment makes sure that the shapes adjacent to the particular shape that are spaced apart from the particular shape by less than the minimum same color spacing have different colors.
Some EDA tools model each shape in a design layout as a node in a graph. Two nodes are connected when the corresponding shapes are apart from each other at a distance smaller than the minimum same color spacing. After this modeling process, the layout is represented as clusters of graphs in which nodes are connected. Each node in a graph is assigned a color in such a way to make sure that the neighboring nodes have different colors. This is because when the neighboring nodes (e.g., a connected pair of nodes) have the same color, the corresponding shapes would violate a design rule that requires two shapes with the same color are apart from each other at a distance greater than or equal to the minimum same color spacing. However, when the nodes in a graph form a loop and there are an odd number of nodes in such graph, it is not possible to assign different colors to all pairs of nodes of the graph.
FIG. 4 illustrates a graph 405 that has three nodes that form such a loop. The graph 405 represents shapes 1-3 in a layer of a design layout 400. This figure illustrates three different color assignments 401-403 to show that it is not possible to assign different colors to adjacent nodes in a graph that has an odd number of nodes forming a loop. Nodes 1-3 of the graph 405 represent the shapes 1-3, respectively. Two different colors, a first color and a second color, are assigned to the shapes 1-3. The first color is depicted as gray and the second color is white in this example. This figure also illustrates a minimum same color spacing 410 depicted as a horizontal line with two ends having vertical bars. As shown, shape 3 is depicted as three connected rectangles. These three rectangles are connected by design and treated as one shape. The shapes depicted in the figures of this application shown as multiple connected rectangles are treated as one shape.
The shapes 1 and 2 are violating the pitch requirement. That is, the two shapes are apart from each other at a distance smaller than the minimum same color spacing 410. So are the shapes 2 and 3. So are the shapes 3 and 1 because the bottom portion of shape 3 is apart from the shape 2 at a distance smaller than the minimum same color spacing 410. Accordingly, the nodes 1-3 of the graph 405 are connected to each other, resulting in a loop. The three different colors assignments 401-403 show the three possible ways of assigning two different colors to the nodes 1-3 and the corresponding shapes 1-3. As shown, no matter how the color assignment is done, one pair of neighboring nodes has the same color. That is, there is always going to be a pair of shapes that would be violating the design rule.
FIG. 5 illustrates an example printing error that is materialized on the physical wafer when the three shapes 1-3 illustrated in FIG. 4 are sent to two different masks. Specifically, this figure shows a possible pattern 530 resulting from applying the color assignment 402 described above. As shown, the shapes 1-3 are divided into two sets of shapes 510 and 515 according to the color assignment 402. That is, the shape 2 is sent to the first of the two masks and the shapes 1 and 3 are sent to the second mask.
Each set of shapes is printed during an exposure of a double exposure photolithographic printing process (e.g., a DPL process). That is, the shape set 510 (i.e., the shape 2) is printed during the first exposure in order to produce contours 520 and the shape set 515 is printed during the second exposure in order to produce contours 525. However, because the shape 1 and the shape 3 were too close (e.g., within the minimum same color spacing 410) in the pattern 505, the contour for the shape 1 and the contour for shape 2 intersect in this example, resulting in a short. The resulting union of the contours 520 and 525 generates the pattern 530. As shown, the pattern 530 did not meet the specifications within the original design layout represented by the pattern 505 in which shapes 1 and 3 are not meant to connect to each other.
Using DPL techniques creates a new challenge for the layout designers because the designers have to satisfy the requirements of DPL techniques in addition to Design Rule Checking (DRC) and Design For Manufacturability (DFM) requirements. Moreover, fixing a double patterning (DP) loop violation is much more complex than fixing a DRC violation. This is because a DRC violation is usually a violation caused by a single shape or interaction of a few shapes whereas a DP loop violation is a set of spacing constraint violations between three or more shapes. It is also relatively more difficult to figure out whether moving a shape to fix a DP loop violation results in a new DP loop violation.
There are several existing approaches that address DP loop violations. One of the approaches is editing layouts manually. This approach is time and manpower intensive because the designers have to go through several iterations of edits to figure out the problems and fix them. Thus, this approach has to rely on skills of the designers in finding a solution to a DP loop violation, which is not as straightforward as finding a solution for a DRC violation.
Another of the existing approaches is an automatic Rip and Reroute technique. The Rip and Reroute technique rips the shapes and reroutes the shapes to resolve a design rule violation. The Rip and Reroute technique uses a minimum same color spacing as a spacing constraint. That is, this technique separates the shapes in a design layout such that all shapes are apart from one another at a distance greater than or equal to a minimum same color spacing. Using this technique therefore results in separating two shapes that have different colors at a distance that is greater than a distance at which shapes with different colors should be apart from each other.
Some Rip and Reroute techniques may be track-based. When the technique is track-based, the technique assigns different colors to predefined tracks. Thus, track-based Rip and Reroute technique may not fully utilize all available space in the design layout because the shapes may not occupy all available track spaces. In addition, the Rip and Reroute technique is computation-intensive and slow because the shapes have to be ripped and rerouted. Also, this technique is of limited use for full custom layouts because the technique modifies existing routing topology to fix a design violation. Finally, the technique also requires connectivity information in the layout.